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1 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 description pin-for-pin, plug-in compatible to the on semiconductor mc100ep196 maximum frequency > 2.5ghz programmable range: 2.2ns to 12.2ns 10ps increments 30ps fine tuning range pecl mode operating range: v cc = 3.0v to 5.5v with v ee = 0v necl mode operating range: v cc = 0v with v ee = C3.0v to C5.5v open input default state safety clamp on inputs a logic high on the /en pin will force q to logic low d[0:10] can accept either ecl, cmos, or ttl inputs v bb output reference voltage available in a 32-pin tqfp package features 3.3v/5v 2.5ghz programmable delay with fine tune control ecl pro? sy100ep196v applications clock de-skewing timing adjustment aperture centering rev.: e amendment: /0 issue date: july 2006 micrel semiconductor on semiconductor sy100ep196vti mc100ep196fa sy100ep196vtitr mc100ep196far2 cross reference table the sy100ep196v is a programmable delay line, varying the time a logic signal takes to traverse from in to q. this delay can vary from about 2.2ns to about 12.2ns. the input can be pecl, lvpecl, necl, or lvnecl. the delay varies in discrete steps based on a control word presented to sy100ep196v. the 10-bit width of this latched control register allows for delay increments of approximately 10ps. in addition, delay may be varied continuously in about a 30ps range by setting the voltage at the ftune pin. an eleventh control bit allows the cascading of multiple sy100ep196v devices, for a wider delay range. each additional sy100ep196v effectively doubles the delay range available. for maximum flexibility, the control register interface accepts cmos or ttl level signals, as well as the input level at the in pins. all support documentation can be found on micrels web site at: www.micrel.com. typical applications circuit typical performance in control logic data signal of unknown phase clock+ clockC /in q /q ftune d ck q+ qC d[9:0] sy100ep196v flip-flop fine tune voltage 0 2000 4000 6000 8000 10000 12000 0 200 400 600 800 1000 1200 delay (ps) tap (digital word) delay vs. tap ecl pro is a registered trademark of micrel, inc. ecl pro ?
2 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 package/ordering information vee d4 d5 d6 d7 d3 d2 d1 vcc setmax setmin len vee /cascade cascade /en vee d0 vcc q /q vcc vcc ftune d8 d9 d10 in /in vbb vef vcf 32 31 30 29 28 27 26 25 910111 213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32-pin tqfp (t32-1) functional block diagram

!" !" # $$ # # ordering information (1) package operating package lead part number type range marking finish sy100ep196vti t32-1 industrial sy100ep196v sn-pb sy100ep196vtitr (2) t32-1 industrial sy100ep196v sn-pb sy100ep196vtg (3) t32-1 industrial sy100ep196v with pb-free pb-free bar-line indicator nipdau sy100ep196vtgtr (2, 3) t32-1 industrial sy100ep196v with pb-free pb-free bar-line indicator nipdau notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs.
3 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 pin number pin name pin function 23, 25, 26, 27, 29, d[0:9] cmos, ecl, or ttl select inputs: these digital control signals adjust the amount of 30, 31, 32, 1, 2 delay from in to q. please refer to the ac electrical table (page 3) and table 7 (page 17) for delay values. figure 9 shows how to interface these inputs to various logic family standards. these inputs default to logic low when left unconnected. bit 0 is the least significant bit, and bit 9 is the most significant bit. 3 d[10] cmos, ecl, or ttl select input: this input latches just like d[0:9] does. it drives the cascade, /cascade differential pair. use only when cascading two or more sy100ep196v to extend the range of delays required. 4, 5 in, /in ecl input: this is the signal to be delayed. if this input pair is left unconnected, this is equivalent to a logic low input. 6 vbb voltage output reference: when using a single-ended logic source for in and /in, connect the unused input of the differential pair to this pin. this pin can also re-bias ac- coupled inputs to in and /in. when used, de-couple this pin to v cc through an 0.01 f capacitor. limit current sinking or sourcing to 0.5ma or less. 7 vef voltage output: connect this pin to vcf when the d inputs are ecl. refer to the digital control logic standard section of the functional description to interface the d inputs to cmos or ttl. 8 vcf voltage input: the voltage at this pin sets the logic transition threshold for the d inputs. 9, 24, 28 vee most negative supply. supply ground for pecl systems. 10 len ecl control input: when logic low, the d inputs flow through. any changes to the d inputs reflect in the delay between in, /in and q, /q. when logic high, the logic values at d are latched, and these latched bits determine the delay. 11 setmin ecl control input: when logic high, the contents of the d register are reset. this sets the delay to the minimum possible, equivalent to d[0:9] being set to 0000000000. when logic low, the value of the d register, or the logic value of setmax determines the delay from in, /in to q, /q. this input defaults to logic low when left unconnected. 12 setmax ecl control input: when logic high and setmin is logic low, the contents of the d register are set high, and the delay is set to one step greater than the maximum possible with d[0:9] set to 1111111111. when logic low, the value of the d register, or the logic value of setmin determines the delay from in, /in to q, /q. this input defaults to logic low when left unconnected. 13, 18, 19, 22 vcc most positive supply: supply ground for necl systems. bypass to v ee with 0.1 f and 0.01 f low esr capacitors. 14, 15 cascade, 100k ecl outputs: these outputs are used when cascading two or more sy100ep196v to /cascade extend the delay range required. refer to table 7 (page 17) for delay values. 16 /en ecl control input: when set active low, q, /q are a delayed version of in, /in. when set inactive high, in, /in are gated such that q, /q become a differential logic low. this input defaults to logic low when left unconnected. 17 ftune voltage control input: by varying the voltage at this pin from v cc through v ee , the delay may be fine tuned by approximately 15ps. leave pin floating if not used. 20, 21 q, /q 100k ecl outputs: this signal pair is the delayed version of in, /in. pin description
4 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) pecl mode (v ee =0v) ............................. C0.5v to +6.0v supply voltage (v ee ) necl mode (v cc =0v) ............................ +0.5v to C6.0v any input voltage (v in ) pecl mode ....................................... C0.5v to v cc +0.5v necl mode ....................................... +0.5v to v ee C0.5v ecl output current (i out ) continuous ............................................................. 50ma surge .................................................................... 100ma i bb sink/source current .......................................... 0.5ma lead temperature (soldering, 20 sec.) ................... +260 c storage temperature (t s ) ....................... C65 c to +150 c esd rating (3) ........................................................... >1.5kv operating ratings (2) supply voltage (v cc ) pecl mode (v ee =0v) ............................. +3.0v to +5.5v supply voltage (v ee ) necl mode (v cc =0v) ............................ C3.0v to C5.5v ambient temperature (t a ) ......................... C40 c to +85 c package thermal resistance tqfp-32 ( ja ) still-air ............................................................. 50 c/w 500lfpm ............................................................ 42 c/w tqfp-32 ( jc ) ..................................................... 20 c/w t a = C40 c to +85 c symbol parameter condition min typ max units v cc power supply voltage (pecl) 3.0 3.3 3.6 v 4.5 5.0 5.5 v v ee power supply voltage (necl) C3.6 C3.3 C3.0 v C5.5 C5.0 C4.5 v i ee power supply current (4) no load, over supply voltage 150 175 ma notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. devices are esd sensitive. handling precautions recommended. 4. required 500lfpm air flow when using +5v or C5v power supply. dc electrical characteristics
5 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 v cc = 3.3v, v ee = 0v; t a = C40 c to +85 c (5, 6) symbol parameter condition min typ max units v oh output high voltage figures 2, 3, 6 2155 2280 2405 mv v ol output low voltage figures 2, 3, 6 1355 1480 1605 mv v ih input high voltage figures 1, 4 pecl 2075 2420 mv cmos 1815 mv ttl 2000 mv v il input low voltage figures 1, 4 pecl 1355 1675 mv cmos 1485 mv ttl 800 mv v bb output voltage reference 1775 1875 1975 mv v cf input select voltage 1610 1720 1825 mv v ef mode connection 1900 2000 2100 mv v ihcmr input high voltage common figure 5 2.0 3.3 v mode range (7) i ih input high current 150 a i il input low current in 0.5 a /in C150 a notes: 5. device is guaranteed to meet the dc specifications, shown in the table above, after thermal equilibrium has been established. the device is tested in a socket such that transverse airflow of 500lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +0.3v to C2.2v. 7. v ihcmr maximum varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. (100kep) lvpecl dc electrical characteristics
6 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 v cc = 5.0v, v ee = 0v; t a = C40 c to +85 c (8, 9) symbol parameter condition min typ max units v oh output high voltage figures 2, 3, 6 3855 3980 4105 mv v ol output low voltage figures 2, 3, 6 3055 3180 3305 mv v ih input high voltage figures 1, 4 pecl 3775 4120 mv cmos 2750 mv ttl 2000 mv v il input low voltage figures 1, 4 pecl 3055 3375 mv cmos 2250 mv ttl 800 mv v bb output voltage reference 3475 3575 3675 mv v ihcmr input high voltage common figure 5 2.0 5.0 v mode range (10) i ih input high current 150 a i il input low current in 0.5 a /in C150 a (100kep) pecl dc electrical characteristics v cc = 0v, v ee = C5.5v to C3.0v; t a = C40 c to +85 c (8) symbol parameter condition min typ max units v oh output high voltage figures 2, 3 C1145 C1020 C895 mv v ol output low voltage figures 2, 3 C1945 C1820 C1695 mv v ih input high voltage necl figures 1, 4 C1225 C880 mv v il input low voltage necl figures 1, 4 C1945 C1625 mv v bb output voltage reference C1525 C1425 C1325 mv v ihcmr input high voltage common figure 5 v ee +2.0 0.0 v mode range (11) i ih input high current 150 a i il input low current in 0.5 a /in C150 a notes: 8. device is guaranteed to meet the dc specifications, shown in the table above, after thermal equilibrium has been established. the device is tested in a socket such that transverse airflow of 500lfpm is maintained. 9. input and output parameters vary 1:1 with v cc . v ee can vary +2.0v to C0.5v. 10. v ihcmr maximum varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 11. v ihcmr minimum varies 1:1 with v ee . the v ihcmr range is referenced to the most positive side of the differential input signal. (100kep) necl dc electrical characteristics
7 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics v cc = 3.0 to 5.5v, v ee = 0v or v cc = 0v, v ee = C3.0 to C5.5v; t a = C40 c to +85 c (12, 13) t a = C40 ct a = +25 ct a = +85 c symbol parameter min typ max min typ max min typ max unit f max maximum frequency (14) 2.5 2.5 2.5 ghz t pd propagation delay in to q; d[0-10]=0 1650 2000 2450 1800 2050 2600 1950 2250 2750 ps in to q; d[0-10]=1023 9500 11500 13500 9800 12200 14000 10600 13300 15800 ps /en to q: d[0-10]=0 1600 2150 2600 1800 2300 2800 2000 2500 3000 ps d10 to cascade 300 420 500 325 450 550 325 525 625 ps t range programmable range t pd (max)-t pd (min) 7850 9450 8200 10000 8850 10950 ps ? t step delay (15) d0 high 9 10 10 ps d1 high 25 26 27 ps d2 high 42 42 43 ps d3 high 75 80 81 ps d4 high 142 143 150 ps d5 high 296 300 310 ps d6 high 532 540 565 ps d7 high 1080 1095 1140 ps d8 high 2100 2150 2250 ps d9 high 4250 4300 4500 ps lin linearity (16) 10 10 10 %lsb t skew duty cycle skew (17) t phl -t plh 25 ps t s setup time d to len 200 0 200 0 200 0 ps d to in (18) 300 140 300 160 300 180 ps /en to in (19) 300 150 300 170 300 180 ps t h hold time len to d 200 60 200 100 200 80 ps in to /en (20) 400 250 400 280 400 300 ps t r release time /en to in (21) 500 ps setmax to len 400 200 400 250 400 300 ps setmin to len 350 275 350 200 350 335 ps t jit cycle-to-cycle jitter (22) 0.2 < 1 0.2 < 1 0.2 < 1 ps rms v pp input voltage swing (differential) 150 800 1200 150 800 1200 150 800 1200 mv t r output rise/fall time t f 20% to 80% (q) 180 250 210 300 230 325 ps 20% to 80% (cascade) 180 250 210 300 230 325 ps notes: 12. ac characteristics are guaranteed by design and characterization. 13. measured using 750mv source, 50% duty cycle clock source. 14. refer to typical operating characteristics for output swing performance. 15. the delays of the individual bits are cumulative. 16. linearity is the deviation from the ideal delay. 17. duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding output edge. 18. setup time defines the amount of time prior to an edge on in, /in that the d[0:9] bits must be set to guarantee the new dela y will occur for that edge. 19. setup time is the minimum that /en must be asserted prior to the next transition of in, /in to prevent an output response gr eater than 75mv to that in, /in transition. 20. hold time is the minimum time that /en must remain asserted after a negative going in or a positive going /in to prevent an output response greater than 75mv to that in, /in transition. 21. release time is the minimum time that /en must be deasserted prior to the next in, /in transition to ensure an output respon se that meets the specified in to q propagation delay and transition times. 22. this is the amount of generated jitter added to an otherwise jitter free clock signal, going from in, /in to q, /q, where th e clock may be any frequency between 0.0 and 2.5ghz.
8 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics 0 100 200 300 400 500 600 700 800 0 500 1000 1500 2000 2500 3000 output swing (mv) frequency (mhz) q, /q output swing vs. frequency 0 20 40 60 80 100 120 140 160 180 -40 -20 0 20 40 60 80 100 i ee (ma) temperature ( c) supply current vs. temperature v cc = 5.5v v cc = 5.0v v cc = 3.3v v cc = 3.0v -25 -20 -15 -10 -5 0 5 10 15 0 0.5 1 1.5 2 2.5 3 3.5 delay (ps) ftune voltage (v) propagation delay vs. ftune voltage C40 85 25
9 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 figure 1a. differential input structure v cc /en len setmin setmax d[0:10] sy100ep196v v bb 75k figure 1b. single-ended input structure v cc q, cascade /q, /cascade sy100ep196v figure 2. emitter output structure v oh v ol 0v q /q cascade /cascade figure 3a. output levels, pecl, lvpecl v oh v ol 0v q /q cascade /cascade figure 3b. output levels, necl
10 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 invalid invalid invalid v cc v ih(max) v ih(min) v il(max) logic high v il(min) 0v logic low figure 4a. input levels, pecl invalid invalid invalid v cc v ih(min) v il(max) logic high 0v logic low figure 4b. input levels, cmos, ttl invalid invalid invalid 0v v ih(max) v ih(min) v il(max) logic high v il(min) v ee logic low figure 4c. input levels, necl v ihcmr 0v in /in figure 5a. input common mode, pecl, lvpecl v ihcmr v ihcmr 0v in /in figure 5b. input common mode, necl
11 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 r2 82 ? r2 82 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc C2v r1 130 ? r1 130 ? +3.3v figure 6a. parallel terminationthevenin equivalent note: 1. for +5.0v systems: r1 = 82 ? , r2 = 130 ? . z = 50 ? z = 50 ? 50 ? 50 ? 50 ? +3.3v +3.3v source destination r b c1 (optional) 0.01 f figure 6b. three-resistor y-termination notes: 1. power-saving alternative to thevenin termination. 2. place termination resistors as close to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . for +3.3v systems r b = 46 ? to 50 ? . for +5v systems, r b = 110 ? . +3.3v +3.3v z o = 50 ? r2 82 ? +3.3v +3.3v r1 130 ? r1 130 ? r2 82 ? v t = v cc C2v q /q 50 ? +3.3v 0.01 f v bb figure 6c. terminating unused i/o notes: 1. unused output (/q) must be terminated to balance the output. 2. micrel's differential i/o logic devices include a v bb reference pin . 3. connect unused input through 50 ? to v bb . bypass with a 0.01 f capacitor to v cc , not gnd, as pecl is referenced to v cc . terminating pecl
12 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 pecl output v bb v cc sy100ep196v in 0.01 f /in figure 7a. interfacing to a single-ended pecl signal pecl output v bb v cc sy100ep196v in 0.01 f /in figure 7b. interfacing to and inverting a single-ended pecl signal 50 50 v bb sy100ep196v in /in v cc 0.01 f figure 8. re-biasing an ac-coupled signal v ef v cf sy100ep196v d[0:10] pecl signals v cc +5.0v v ee 0v figure 9a. connecting pecl signals to the d inputs v ef v cf sy100ep196v d[0:10] l vpecl signals v cc +3.3v v ee 0v figure 9b. connecting lvpecl signals to the d inputs v ef v cf nc nc sy100ep196v d[0:10] cmos inputs v cc +3.3v or +5.0v v ee 0v figure 9c. connecting cmos signals to the d inputs note: v cf and v ef are not connected v ef nc v cf sy100ep196v d[0:10] ttl inputs v cc +3.3v v ee 0v 0v 1.5k figure 9d. connecting ttl signals to the d inputs with v cc = 3.3v v ef nc v cf sy100ep196v d[0:10] ttl inputs v cc +5.0v v ee 0v 0v 500 figure 9e. connecting ttl signals to the d inputs with v cc = 5.0v
13 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 functional description sy100ep196v is a programmable delay line, varying the delay of a pecl or necl input signal by any amount between about 2.2ns and 12.2ns. a 10-bit digital control register affords delay steps of approximately 10ps. sy100ep196v implements the delay using a multiplexer chain and a set of fixed delay elements. under digital control, various subsets of the delay elements are included in the signal chain. to simplify interfacing, the 10-bit digital delay control word interfaces to pecl, cmos, or ttl interface standards. since multiplexers must appear in the delay path, sy100ep196v has a minimum delay of about 2.2ns. delays below this value are not possible. in addition, when cascading multiple sy100ep196v to extend the delay range, the minimum delay is about 2.2ns times the number of sy100ep196v in cascade. an eleventh control bit, d[10], along with the cascade and /cascade outputs and the setmin and setmax inputs, simplifies the task of cascading. signal path logic standard the signal path, from in, /in to q, /q, interfaces to pecl, lvpecl, or necl signals, as shown in table 6. the choice of signal path logic standard may limit possible choices for the delay control inputs, d. input enable the /en input gates the signal at in, /in. when disabled, the input is effectively gated out, just as if a logic low was being provided to sy100ep196v. /en value at q, /q l in, /in delayed h logic low delayed table 1. /en truth table digital control latch sy100ep196v can capture the digital delay control word into its internal 11-bit latch, 10 bits for d[0:9], and an extra bit for the d[10] cascade control. the len input controls the action of this latch, as per table 2. note that the len input is always pecl, lvpecl, or necl, the same as the in, /in signal pair. the 11-bit delay control word, however, may also be cmos or ttl. len latch action l pass through d[0:10] h latch d[0:10] table 2. len truth table the nominal delay value is based on the binary value in d[0:9], where d[0] is the least significant bit, and d[9] is the most significant bit. this delay from in, /in to q, /q is about: ? t 2200 10 value d 9:0 + delay ftune ,ps =+ [] () () digital control logic standard when used in systems where v ee connects to ground, sy100ep196v may interface either to pecl, cmos, or ttl on its d[0:10] inputs. to this end, the vcf pin sets the threshold at which the d inputs switch between logic low and logic high. as shown in table 3, connecting v cf to v ef sets the threshold to pecl (if v cc is 5v) or lvpecl (if v cc is 3.3v). leaving v cf and v ef open yields a threshold suitable for detecting cmos output logic levels. leaving v ef open and connecting v cf to a 1.5v source allows the d inputs to accept ttl signals. logic standard v cf connects to ecl, pecl vef cmos no connect ttl 1.5v source table 3. digital control standard truth table if a 1.5v source is not available, connecting v cf to v ee through an appropriate resistor will bias v cf at about 1.5v. the value of this resistor depends on the v cc supply, as indicated in table 4. v cc resistor value 3.3v 1.5k ? 5.0v 500 ? table 4. resistor values for ttl input cascade logic sy100ep196v is designed to ease cascading multiple devices in order to achieve a greater delay range. the setmin and setmax pins accomplish this, as set out in the applications section below. setmin and setmax override the delay by changing the value in the d latch register. table 5 lists the action of these pins. setmin setmax nominal delay (ps) ll as per d latch lh 2200 + 10 1024 hl 2200 hh not allowed table 5. setmin and setmax action
14 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 signal path logic standard v cc v ee delay control input choices pecl +4.5v to +5.5v 0v pecl, cmos, ttl lvpecl +3.0v to +3.6v 0v lvpecl, cmos, ttl necl 0v C3.0 to C5.5v necl table 6. signal path logic standard fine tune control in addition to the digital delay control, the ftune input permits a continuous variation in delay. though it may be set to any voltage between v cc and v ee , most of the delay variation occurs between v ee and v ee + 1.5v. refer to typical operating characteristics. for convenience, a v cc of 3.3v is assumed. typically, the ftune input will be fed by a dac whose purpose is to provide extremely fine delay under digital control.
15 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 for best performance, use good high frequency layout techniques, filter v cc supplies, and keep ground connections short. use multiple vias where possible. also, use controlled impedance transmission lines to interface with the sy100ep196v data inputs and outputs. v bb supply the vbb pin is an internally generated supply, and is available for use only by the sy100ep196v. when unused, this pin should be left unconnected. the two common uses for v bb are to handle a single-ended pecl input, and to re- bias inputs for ac-coupling applications. if in, /in is driven by a single-ended output, v bb is used to bias the unused input. please refer to figures 9. the pecl signal driving sy100ep196v may optionally be inverted in this case. when the signal is ac-coupled, v bb is used, as shown in figure 10, to re-bias in, /in. this ensures that sy100ep196v inputs are within its acceptable common mode range. in all cases, v bb current sinking or sourcing must be limited to 0.5ma or less. applications information setting d input logic thresholds as explained earlier, in all designs where the sy100ep196v v ee supply is at zero volts, the d inputs may accommodate cmos and ttl level signals, as well as pecl or lvpecl. figures 9 show how to connect v cf and v ef for all possible cases. cascading two or more sy100ep196v may be cascaded, in order to extend the range of delays permitted. each additional sy100ep196v adds about 2200ps to the minimum delay, and adds another 10240ps to the delay range. internal cascade circuitry has been included in the sy100ep196v. using this internal circuitry, sy100ep196v may be cascaded without any external gating. examples of cascading 2, 3, or 4 sy100ep196v appear in figures 10. table 7 lists the nominal delay for all the cases that appear in figures 10. in /in q /q in /in q ftune ftune /q d[9:0] sy100ep196v sy100ep196v #2 #1 setmin setmax /cascade cascade d[10] c[9:0] c[10] control word (11bits) dac figure 10a. cascading two sy100ep196v in /in q /q in /in q /q sy100ep196v sy100ep196v #3 dac #2 setmin setmax setmin setmax /cascade cascade d[10] c[11] in /in q ftune ftune /q d[9:0] sy100ep196v #1 /cascade cascade d[10] c[9:0] c[10] control word (12bits) figure 10b. cascading three sy100ep196v
16 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 in /in q /q in /in q /q sy100ep196v sy100ep196v setmin setmax setmin setmax /cascade cascade d[10] c[11] in /in q /q sy100ep196v setmin setmax in /in q ftune ftune /q d[9:0] sy100ep196v /cascade cascade d[10] c[9:0] c[10] control word (12bits) dac figure 10c. cascading four sy100ep196v part number function data sheet link sy100ep195vti 3.3v/5v 2.5ghz programmable delay chip http://www.micrel.com/product-info/products/sy100ep195v.shtml sy55856uhi 2.5v/3.3v 2.5ghz differential 2-channel http://www.micrel.com/product-info/products/sy55856u.shtml precision cml delay line related product and support documentation
17 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 control inputs nominal delay (ps) d[11] d[10] d[9:0] one chip two chips three chips four chips 00 0000000000 2,200 4,400 6,600 8,800 00 0000000001 2,210 4,410 6,610 8,810 00 0000000010 2,220 4,420 6,620 8,820 00 0000000100 2,240 4,440 6,640 8,840 00 0000001000 2,280 4,480 6,680 8,880 00 0000010000 2,360 4,560 6,760 8,960 00 0000100000 2,520 4,720 6,920 9,120 00 0001000000 2,840 5,040 7,240 9,440 00 0010000000 3,480 5,680 7,880 10,080 00 0100000000 4,760 6,960 9,160 11,360 00 1000000000 7,320 9,520 11,720 13,920 00 1111111111 12,430 14,630 16,830 19,030 01 0000000000 14,640 16,840 19,040 01 0000000001 14,650 16,850 19,050 01 0000000010 14,660 16,860 19,060 01 0000000100 14,680 16,880 19,080 01 0000001000 14,720 16,920 19,120 01 0000010000 14,800 17,000 19,200 01 0000100000 14,960 17,160 19,360 01 0001000000 15,280 17,480 19,680 01 0010000000 15,920 18,120 20,320 01 0100000000 17,200 19,400 21,600 01 1000000000 19,760 21,960 24,160 01 1111111111 24,870 27,070 29,270 10 0000000000 27,080 29,280 10 0000000001 27,090 29,290 10 0000000010 27,100 29,300 10 0000000100 27,120 29,320 10 0000001000 27,160 29,360 10 0000010000 27,240 29,440 10 0000100000 27,400 29,600 10 0001000000 27,720 29,920 10 0010000000 28,360 30,560 10 0100000000 29,640 31,840 10 1000000000 32,200 34,400 10 1111111111 37,310 39,510 11 0000000000 27,080 39,520 11 0000000001 27,090 39,530 11 0000000010 27,100 39,540 11 0000000100 27,120 39,560 11 0000001000 27,160 39,600 11 0000010000 27,240 39,680 11 0000100000 27,400 39,840 11 0001000000 27,720 40,160 11 0010000000 28,360 40,800 11 0100000000 29,640 42,080 11 1000000000 32,200 44,640 11 1111111111 37,310 49,750 table 7. list of nominal delay values for cascaded sy100ep196v
18 ecl pro? sy100ep196v micrel, inc. m9999-072706 hbwhelp@micrel.com or (408) 955-1690 rev. 01 32-pin tqfp (t32-1) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is at purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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